Analog-to-digital converters (ADCs) are in widespread use today in electronic applications for consumer, medical, industrial, etc. Typically, ADCs include circuitry for receiving an analog input signal and outputting a digital value proportional to the analog input signal. This digital output value is typically in the form of either a parallel word or a serial digital bit string. There are many types of analog-to-digital conversion schemes such as voltage-to-frequency conversion, charge redistribution, delta modulation, as well as others. Typically, each of these conversion schemes has its advantages and disadvantages.
One type of analog-to-digital converter (ADC) that has seen increasing use is the switched capacitor sigma-delta ADC (sigma-delta and delta-sigma will be used interchangeably herein). The sigma-delta ADC utilizes delta-sigma modulation where an analog voltage is input to the delta-sigma modulator and the output thereof is filtered to remove noise. A delta-sigma modulator typically converts an analog input to a digital serial string of “ones” and “zeros” having an average amplitude over time proportional to the analog input. Delta-sigma modulation generally provides for high accuracy and wide dynamic range as compared to earlier delta modulation techniques. Delta-sigma modulation is often referred to as an oversampled converter architecture and is typically immune from some of the earlier undesirable second order effects of delta modulation.
The switched capacitor sigma-delta converter uses a digital-to-analog converter (DAC) in a feedback loop that applies a voltage(s) to an analog summing node located at the front end (analog portion) of the delta-sigma modulator. With any ADC there are a number of noise sources that are inherent in the ADC design. In a typical delta-sigma ADC, there are typically three types of noise: the quantization noise coming from the error introduced by the quantizer in the feedback loop, the thermal noise coming from the devices of the converter itself and the 1/f noise coming also from the devices. In addition, since the output code of the ADC is proportional to the ratio of the input voltage and the reference voltage, any additional noise coming from the reference voltage will be present at the output especially when the ratio of the input voltage over reference voltage is close to 1. Moreover, a deterministic error in the voltage reference coming from a DC offset will impact the ADC as a gain error.
The quantization noise at low frequencies is relatively low with the largest portion thereof existing at higher frequencies. This higher frequency portion noise can be filtered out by a digital domain filter, e.g., decimation and/or digital low-pass filter. Moreover, the quantization noise can be lowered by increasing either the order of the modulator or the resolution of the DAC. The thermal noise coming from both the reference voltage and the ADC can be averaged by increasing the oversampling ratio of the converter. However, averaging techniques do not filter DC offset and 1/f noise, especially when they come from the voltage reference, as they are typically passed through the converter with the signal information. For high-resolution ADCs, 1/f noise becomes the dominant one when both quantization and thermal noise have been reduced. It is very difficult to attenuate since it is not affected by increasing complexity of the ADC (higher order, multi-bit DAC) or the oversampling.
DC offset from the voltage reference may be substantially reduced by using a chopper stabilized voltage reference. A typical chopper stabilized bandgap voltage reference is more fully described in U.S. Pat. No. 6,462,612, entitled “Chopper Stabilized Bandgap Reference Circuit to Cancel Offset Variation” by Roh et al., and is incorporated by reference herein for all purposes. The chopper stabilized voltage reference substantially reduces direct current (DC) offset voltage error in the voltage reference. However, the typical chopper stabilized voltage reference requires an analog low-pass filter at the output of the reference to remove the components of the high-frequency modulation introduced by the chopper stabilization. Such a low pass filter isn't required when the chopped Bandgap voltage is directly applied to the reference input of a sigma-delta converter: the HF chopping noise can be filtered out by the decimation and/or digital low-pass filter. However, a modified chopper sequence is required when the decimation and/or digital low-pass filter is used for filtering out HF chopping noise. FIG. 12 shows the errors produced by a 5-level DAC with conventional chopper algorithm. As can be seen, huge spikes appear when the bit stream and chopper control frequency correlation is high.
A sigma-delta analog-to-digital converter (ADC) may use a multibit DAC in the modulator loop. This has advantages in terms of resolution, signal to noise ratio and brings improvements regarding stability at a reduced cost in terms of design complexity and power consumption. However, linearity is often degraded by a multi-bit DAC that is not inherently linear and often requires very accurate calibration and/or trimming.
On the other hand, the voltage references used by the ADC often contribute significantly to the noise figure of the system, especially on low bandwidth systems because of the 1/f noise that is not removed with oversampling technique. Moreover, the offset of the amplifier in the voltage reference circuit contributes to gain error of the ADC and often requires trimming or calibration.